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Reduction of image coding artifacts using spatial structure analysis.

, , , and . ISSPA, page 1-4. IEEE, (2007)

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A modularized 3D heterogeneous system integration platform., , , , , , , , and . APCCAS, page 396-399. IEEE, (2012)Implementation and Prototyping of a Complex Multi-project System-on-a-chip., , , , , , , and . ISCAS, page 2321-2324. IEEE, (2009)VLSI architecture of extended in-place path metric update for Viterbi decoders., , , and . ISCAS (4), page 206-209. IEEE, (2001)Efficient path metric access for reducing interconnect overhead in Viterbi decoders., , , and . ISCAS, IEEE, (2006)Low-complexity Reed-Solomon decoder for optical communications., , and . ISCAS, page 4173-4176. IEEE, (2010)PrSoC: Programmable System-on-chip (SoC) for silicon prototyping., , , and . ISCAS, page 3382-3385. IEEE, (2008)Intraseasonal Vertical Cloud Regimes Based on CloudSat Observations over the Tropics., , , , and . Remote. Sens., 12 (14): 2273 (2020)A high-performance area-aware DSP processor architecture for video codecs., , , , , and . ICME, page 1499-1502. IEEE Computer Society, (2004)An Efficient Multiplier/Divider Design for Elliptic Curve Cryptosystem over GF(2m)., , , and . J. Inf. Sci. Eng., 25 (5): 1555-1573 (2009)Design of high-speed bit-serial divider in GF(2m)., , and . ISCAS, page 713-716. IEEE, (2010)