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A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM., , , , , , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2016)Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential., , , , , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2011)A half-pel precision MPEG2 motion-estimation processor with concurrent three-vector search., , , , , , , , , and . IEEE J. Solid State Circuits, 30 (12): 1502-1509 (December 1995)Multimodal Cardiovascular Information Monitor Using Piezoelectric Transducers for Wearable Healthcare., , , , and . J. Signal Process. Syst., 91 (9): 1053-1062 (2019)Data Transmission Scheduling Based on RTS/CTS Exchange for Periodic Data Gathering Sensor Networks., , , , and . IEICE Trans. Commun., 90-B (12): 3410-3418 (2007)Counter-Based Broadcasting with Hop Count Aware Random Assessment Delay Extension for Wireless Sensor Networks., , , , , and . IEICE Trans. Commun., 91-B (11): 3489-3498 (2008)A 433-MHz Rail-to-Rail Voltage Amplifier with Carrier Sensing Function for Wireless Sensor Networks., , , , , and . IEICE Trans. Electron., 92-C (6): 815-821 (2009)Divided Static Random Access Memory for Data Aggregation in Wireless Sensor Nodes., , , , , , , and . IEICE Trans. Commun., 95-B (1): 178-188 (2012)A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme., , , , , , , , and . IEICE Trans. Electron., 98-C (4): 333-339 (2015)A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation., , , , , , , , , and 4 other author(s). IEICE Trans. Electron., 97-C (4): 332-341 (2014)