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Track-based Translation Layers for Interlaced Magnetic Recording.

, , , and . USENIX ATC, page 821-832. USENIX Association, (2019)

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Enabling Dynamic Heterogeneity Through Core-on-Core Stacking., , , , and . DAC, page 182:1-182:6. ACM, (2014)Minimizing Read Seeks for SMR Disk., , and . IISWC, page 146-155. IEEE Computer Society, (2018)FARHAD: A Fault-Tolerant Power-Aware Hybrid Adder for add intensive applications., , and . ASAP, page 153-159. IEEE Computer Society, (2013)ElasticCore: enabling dynamic heterogeneity with joint core and voltage/frequency scaling., , , , and . DAC, page 151:1-151:6. ACM, (2015)Adaptive Bandwidth Management for Performance-Temperature Trade-offs in Heterogeneous HMC+DDRx Memory., , , , and . ACM Great Lakes Symposium on VLSI, page 391-396. ACM, (2015)μCache: a mutable cache for SMR translation layer., , and . MASCOTS, page 1-8. IEEE, (2020)FSTL: A Framework to Design and Explore Shingled Magnetic Recording Translation Layers., , , and . MASCOTS, page 40-52. IEEE Computer Society, (2018)Realizing complexity-effective on-chip power delivery for many-core platforms by exploiting optimized mapping., , , , , and . ICCD, page 581-588. IEEE Computer Society, (2015)Modeling SMR Drive Performance., , , and . SIGMETRICS, page 389-390. ACM, (2016)D3N: A multi-layer cache for the rest of us., , , , , , , , and . IEEE BigData, page 327-338. IEEE, (2019)