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Disambiguation of "Lee, Chao-Lin"

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Architecture and Compiler Support for GPUs Using Energy-Efficient Affine Register Files.

, , , , and . ACM Trans. Design Autom. Electr. Syst., 23 (2): 18:1-18:25 (2018)

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Wei-Chao Lin

Hsi-Lin Chao

Sabrina Lin Lin Lee

Chia-Lin Lee

Maw-Lin Lee

 

Other publications of authors with the same name

Sparse-Matrix Compression Primitives with OpenCL Framework to Support Halide., , , , and . IWOCL, page 24:1-24:2. ACM, (2019)Support of Sparse Tensor Computing for MLIR HLS., , , and . ICPP Workshops, page 88-95. ACM, (2023)Devise Sparse Compression Schedulers to Enhance FastText Methods., , , , , and . ICPP Workshops, page 4:1-4:8. ACM, (2020)The Rewriting of DataRaceBench Benchmark for OpenCL Program Validations., , , , and . ICPP Workshops, page 15-22. ACM, (2024)Enable the Flow for GPGPU-Sim Simulators with Fixed-Point Instructions., , , and . ICPP Workshops, page 12:1-12:5. ACM, (2018)Support Convolution of CNN with Compression Sparse Matrix Multiplication Flow in TVM., , , , , and . ICPP Workshops, page 17:1-17:7. ACM, (2021)Register-Pressure Aware Predicator for Length Multiplier of RVV., , , , and . ICPP Workshops, page 10:1-10:9. ACM, (2022)Low DRAM Memory Access and Flexible Dataflow Convolutional Neural Network Accelerator based on RISC-V Custom Instruction., , , , , , , , and . ISCAS, page 1-5. IEEE, (2024)Experiments and optimizations for TVM on RISC-V Architectures with P Extension., , , , , , , and . VLSI-DAT, page 1-4. IEEE, (2020)Accelerate Binarized Neural Networks with Processing-in-Memory Enabled by RISC-V Custom Instructions., , , , and . ICPP Workshops, page 15:1-15:8. ACM, (2021)