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Disambiguation of "Yun, Byeonghun"

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Analysis and Design of Power-Efficient H-Band CMOS Frequency Doubler Employing Gain Boosting and Harmonic Enhancing Techniques.

, , , and . IEEE Access, (2023)

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Jong-Mo Yun

Hyong-Sik Yun

Jaeman Yun

Yong-Seon Yun

Bettina Yunis

 

Other publications of authors with the same name

A D-Band Power Amplifier in 65-nm CMOS by Adopting Simultaneous Output Power-and Gain-Matched Gmax-Core., , , , and . IEEE Access, (2021)Analysis and Design of Power-Efficient H-Band CMOS Frequency Doubler Employing Gain Boosting and Harmonic Enhancing Techniques., , , and . IEEE Access, (2023)An LPWAN Radio with a Reconfigurable Data/Duty-Cycled-Wake-Up Receiver., , , , , , , , , and 1 other author(s). ISSCC, page 404-406. IEEE, (2022)Design of High-Gain Sub-THz Regenerative Amplifiers Based on Double-Gmax Gain Boosting Technique., , , , , and . IEEE J. Solid State Circuits, 56 (11): 3388-3398 (2021)A 250-GHz Wideband Direct-Conversion CMOS Receiver Adopting Baseband Equalized Low-Loss Resistive Passive Mixer., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 70 (10): 3852-3856 (October 2023)A 915 MHz, 499 μW, -99 dBm, and 100 kbps BFSK Direct Conversion Receiver., , , , , , , , and . ESSCIRC, page 209-212. IEEE, (2019)A 293/440 GHz Push-Push Double Feedback Oscillators with 5.0/-3.9 dBm Output Power and 2.9/0.6 % DC-to-RF Efficiency in 65 nm CMOS., , , and . VLSI Circuits, page 1-2. IEEE, (2020)H-Band Power Amplifiers in 65-nm CMOS by Adopting Output Power Maximized Gmax-Core and Transmission Line-Based Zero-Degree Power Combining Networks., , and . IEEE J. Solid State Circuits, 58 (11): 3089-3102 (November 2023)29.7 A 490GHz 32mW Fully Integrated CMOS Receiver Adopting Dual-Locking FLL., , , , , and . ISSCC, page 452-454. IEEE, (2020)245/243GHz, 9.2/10.5dBm Saturated Output Power, 4.6/2.8% PAE, and 28/26dB Gain Power Amplifiers in 65nm CMOS Adopting 2-and 4-way Power Combining., , , , and . A-SSCC, page 1-3. IEEE, (2021)