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Understanding the Effect of Process Variations on the Delay of Static and Domino Logic., , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (5): 697-710 (2010)Modeling of Feedback Analog Circuits with VHDL., , , and . ICECS, page 882-885. IEEE, (2006)Exploitation of the phasor approach for closed-form solution of the Van der Pol's oscillator and sinusoidal oscillators with high-order nonlinearity., , and . ICECS, page 155-158. IEEE, (2009)TG Master-Slave FFs: High-speed optimization., , and . ISCAS, page 554-557. IEEE, (2011)A simple keeper topology to reduce delay variations in nanometer domino logic., , and . ISCAS, page 1576-1579. IEEE, (2012)A comparison between amoled poly-TFT driver circuits., and . ICECS, page 1-5. IEEE, (2005)Design guidelines for high-speed Transmission-gate latches: Analysis and comparison., and . ICECS, page 145-148. IEEE, (2008)Tunable Linear MOS Resistors Using Quasi-Floating-Gate Techniques., , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 56-II (1): 41-45 (2009)Analysis and evaluation of harmonic distortion in the tunnel diode oscillator., , and . ISCAS, IEEE, (2006)Distortion analysis in the frequency domain of a Gm-C biquad., , and . ECCTD, page 212-215. IEEE, (2007)