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SoC Scan-Chain verification utilizing FPGA-based emulation platform and SCE-MI interface., , и . SoCC, стр. 398-403. IEEE, (2014)Synthesis scheme for low power designs with multiple supply voltages by tabu search., , и . ISCAS (5), стр. 261-264. IEEE, (2004)Scalable and fault-tolerant network-on-chip design usingthe quartered recursive diagonal torus topology., , , , , и . ACM Great Lakes Symposium on VLSI, стр. 309-314. ACM, (2008)On a Chaotic Neural Network with Decaying Chaotic Noise., , , и . ISNN (1), том 3496 из Lecture Notes in Computer Science, стр. 497-502. Springer, (2005)A Degree Priority Routing Algorithm for Irregular Mesh Topology NoCs., , , и . ICESS, стр. 293-297. IEEE Computer Society, (2008)Building temperature-insensitive nanoscale CMOS circuits with adaptive voltage power supplies., , , и . CCECE, стр. 1-4. IEEE, (2017)Improving the efficiency of thermal covert channels in multi-/many-core systems., , , , , и . DATE, стр. 1459-1464. IEEE, (2018)Fault-Tolerant Routing Schemes in RDT(2, 2, 1)/a-Based Interconnection Network for Networks-on-Chip Designs., , , и . ISPAN, стр. 52-57. IEEE Computer Society, (2005)On self-tuning networks-on-chip for dynamic network-flow dominance adaptation., , , , , и . NOCS, стр. 1-8. IEEE, (2013)Efficient multicast schemes for 3-D Networks-on-Chip., , , , , , и . J. Syst. Archit., 59 (9): 693-708 (2013)