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Disambiguation of "Rhee, Woogeun"

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A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order ΔΣ modulator.

, , and . IEEE J. Solid State Circuits, 35 (10): 1453-1460 (2000)

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Sascha Rhee

Hanjo Rhee

Sora Rhee

Kyu Ho Rhee

Jong Il Rhee

 

Other publications of authors with the same name

A Hybrid Spur Compensation Technique for Finite-Modulo Fractional-N Phase-Locked Loops., , , , , , and . IEEE J. Solid State Circuits, 44 (11): 2922-2934 (2009)A 0.42-mW 1-Mb/s 3- to 4-GHz Transceiver in 0.18-µm CMOS With Flexible Efficiency, Bandwidth, and Distance Control for IoT Applications., , , , and . IEEE J. Solid State Circuits, 52 (6): 1479-1494 (2017)F5: Low-power radios for sensor networks., , , , , and . ISSCC, page 518-519. IEEE, (2014)9.3 A 1mW 1Mb/s 7.75-to-8.25GHz chirp-UWB transceiver with low peak-power transmission and fast synchronization capability., , , , , , and . ISSCC, page 162-163. IEEE, (2014)A 1GHz Fractional-N PLL Clock Generator with Low-OSR ΔΣ Modulation and FIR-Embedded Noise Filtering., , , , and . ISSCC, page 346-347. IEEE, (2008)A 0.6V 50-to-145MHz PVT tolerant digital PLL with DCO-dedicated ΔΣ LDO and temperature compensation circuits in 65nm CMOS., , , , and . ISCAS, page 1-4. IEEE, (2017)A Noise and Spur Reduction Technique for ΔΣ Fractional-N Bang-Bang PLLs with Embedded Phase Domain Filtering., , , and . ISCAS, page 1-4. IEEE, (2019)A 3.5-4GHz FMCW radar transceiver design with phase-domain oversampled ranging by utilizing a 1-bit ΔΣ TDC., , , , , , and . VLSI-DAT, page 1-4. IEEE, (2014)A ΔΣ DPLL with 1b TDC, 4b DTC and 8-tap FIR filter for low-voltage clock generation/modulation systems., , , and . VLSI-DAT, page 1-4. IEEE, (2018)A ΔΣ IR-UWB radar with sub-mm ranging capability for human body monitoring systems., , and . ISCAS, page 1315-1318. IEEE, (2012)