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Pushing the envelope in distributed ns-3 simulations: one billion nodes., , , , and . WNS3, page 67-74. ACM, (2015)Integrating ns-3 model construction, description, preprocessing, execution, and visualization., , , , , , , and . SimuTools, page 176-181. ICST/ACM, (2013)Full-span structural compilation of DSP hardware., , , , , , and . ICASSP, page 495-498. IEEE, (1987)Serial/Parallel architectures for area-efficient vector multiplication., and . ICASSP, page 539-542. IEEE, (1987)Techniques to increase the computational throughput of bit-serial architectures., , and . ICASSP, page 543-546. IEEE, (1987)A comparison of micro-DSP and Silicon compiler implementations of a polyphase network filter bank., , , , , and . ICASSP, page 2207-2210. IEEE, (1986)Synthesis of area-efficient VLSI architectures for vector and matrix multiplication., and . IEEE Symposium on Computer Arithmetic, page 13-20. IEEE Computer Society, (1987)The Multicomputer Toolbox - First-Generation Scalable Libraries., , , , , and . HICSS (2), page 644-654. IEEE Computer Society, (1994)The Parallel Performance of a Groundwater Flow Code on the Cray T3D., , , and . PPSC, page 131-136. SIAM, (1995)S3: the Spectrum Sharing Simulator., , , , , , , and . WNGW@WNS3, page 34-37. ACM, (2019)