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A deep learning approach to spine segmentation using a feed-forward chain of pixel-wise convolutional networks.

, , , , and . ISBI, page 868-871. IEEE, (2018)

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Dynamic intrinsic chip ID using 32nm high-K/metal gate SOI embedded DRAM., , , , , and . VLSIC, page 146-147. IEEE, (2012)A Commercial Field-Programmable Dense eFUSE Array Memory with 99.999% Sense Yield for 45nm SOI CMOS., , , , , , , , , and 1 other author(s). ISSCC, page 406-407. IEEE, (2008)45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications., , , , , , , , , and 10 other author(s). IBM J. Res. Dev., 55 (3): 5 (2011)Integrated neural interfaces., , , , , , , , and . MWSCAS, page 1045-1048. IEEE, (2017)A 16nm 785GMACs/J 784-Core Digital Signal Processor Array With a Multilayer Switch Box Interconnect, Assembled as a 2×2 Dielet with 10μm-Pitch Inter-Dielet I/O for Runtime Multi-Program Reconfiguration., , , and . ISSCC, page 52-54. IEEE, (2022)A Case for Packageless Processors., , , , , and . HPCA, page 466-479. IEEE Computer Society, (2018)Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias., , , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (3): 373-384 (2016)Toward Human-Scale Brain Computing Using 3D Wafer Scale Integration., , , and . JETC, 13 (3): 45:1-45:21 (2017)An 8T eNVSRAM Macro in 22nm FDSOI Standard Logic with Simultaneous Full-Array Data Restore for Secure IoT Devices., and . ISSCC, page 434-435. IEEE, (2023)Large-Scale Quantum System Design on Nb-based Superconducting Silicon Interconnect Fabric., and . ISQED, page 315. IEEE, (2021)