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Другие публикации лиц с тем же именем

Efficient Hardware Implementation of Encoder and Decoder for Golay Code., и . IEEE Trans. Very Large Scale Integr. Syst., 23 (9): 1965-1968 (2015)A high throughput pass parallel block decoder architecture for JPEG 2000 that prevents stalling in the decoding process., и . Integr., (2020)FPGA-accelerated adaptive projection-based image registration., и . J. Real Time Image Process., 18 (1): 113-125 (2021)Design of static and dynamic translinear circuits based on CMOS CCII translinear loops., , , и . ICECS, стр. 1-4. IEEE, (2005)VLSI design of memory-efficient, high-speed baseline MQ coder for JPEG 2000., и . Integr., 45 (1): 1-8 (2012)Motion estimation in medical video sequences using affine transform., и . CBMS, стр. 1-4. IEEE Computer Society, (2012)Real Time Noise Cleaning of Ultrasound Images., , и . CBMS, стр. 379-384. IEEE Computer Society, (2004)Real Time Dynamic Receive Apodization for an Ultrasound Imaging System., , , и . VLSI Design, стр. 534-537. IEEE Computer Society, (2006)An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture., , , , и . ISCAS, стр. 149-152. IEEE, (2008)A Reconfigurable Memory-Based Fast VLSI Architecture for Computation of the Histogram., и . IEEE Trans. Consumer Electronics, 65 (2): 128-133 (2019)