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A sample-time error calibration technique in time-interleaved ADCs with correlation-based detection and voltage-controlled compensation., , , , and . APCCAS, page 128-131. IEEE, (2012)A DLL based low-phase-noise clock multiplier with offset-tolerant PFD., , and . ASICON, page 1-4. IEEE, (2013)On the Secure Degrees of Freedom for Two-User MIMO Interference Channel With a Cooperative Jammer., , and . IEEE Trans. Commun., 67 (8): 5390-5402 (2019)Communication-efficient distributed estimator for generalized linear models with a diverging number of covariates., , , , and . Comput. Stat. Data Anal., (2021)Automatic gain control algorithm with high-speed and double closed-loop in UWB system., , , , and . ASICON, page 1-4. IEEE, (2013)A 7.8 fJ/conversion-step 9-bit 400-MS/s single-channel SAR ADC with fast control logic., , , and . APCCAS, page 42-45. IEEE, (2018)A background time-skew calibration technique in flash-assisted time-interleaved SAR ADCs., , , , and . ASICON, page 295-298. IEEE, (2017)A 13-bit non-binary weighted SAR ADC with bridge structure using digital calibration for capacitor weight error., , and . ASICON, page 32-35. IEEE, (2017)A 15MHz BW continuous-time ΔΣ modulator with high speed digital ELD compensation., , , , and . ASICON, page 686-689. IEEE, (2017)A 4-mW8-b 600-MS/s 2-b-per-cycle SAR ADC with a capacitive DAC., , , , and . ASICON, page 1-4. IEEE, (2013)