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Body bias driven design synthesis for optimum performance per area., и . ISQED, стр. 472-477. IEEE, (2010)Analysis of the Influence of Substrate on the Performance of On-Chip MOS Decoupling Capacitors., и . IEEE J. Solid State Circuits, 44 (2): 484-494 (2009)Technology exploration for adaptive power and frequency scaling in 90nm CMOS., , и . ISLPED, стр. 14-19. ACM, (2004)Reducing Cross-Talk Induced Power Consumption and Delay., , и . PATMOS, том 3254 из Lecture Notes in Computer Science, стр. 179-188. Springer, (2004)CMDS: Cross-layer Dataflow Optimization for DNN Accelerators Exploiting Multi-bank Memories., , , , , , и . ISQED, стр. 1-8. IEEE, (2023)Active Noise Cancellation Using Aggressor-Aware Clamping Circuit for Robust On-Chip Communication., , и . VLSI Design, стр. 325-329. IEEE Computer Society, (2005)An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits., , и . PATMOS, том 3728 из Lecture Notes in Computer Science, стр. 187-196. Springer, (2005)CMDS: Cross-layer Dataflow Optimization for DNN Accelerators Exploiting Multi-bank Memories., , , , , , и . CoRR, (2024)A forward body bias generator for digital CMOS circuits with supply voltage scaling., , , , , , и . ISCAS, стр. 2482-2485. IEEE, (2010)Glitch-free discretely programmable clock generation on chip., , и . ISCAS (2), стр. 1839-1842. IEEE, (2005)