( en | de | ru )

 

Disambiguation of "Nambiar, Vishnu P."

Author of the publication

copydeleteadd this publication to your clipboard
Co-simulation methodology for improved design and verification of hardware neural networks.

, , and . IECON, page 2226-2231. IEEE, (2013)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Raghu Nambiar

Sandeep Nambiar

Smitha Vishnu

Vishnu Kotrajaras

Vishnu Bendre

 

Other publications of authors with the same name

Accelerating the AES encryption function in OpenSSL for embedded systems., , and . Int. J. Inf. Commun. Technol., 2 (1/2): 83-93 (2009)Block-Based Spiking Neural Network Hardware with Deme Genetic Algorithm., , , and . ISCAS, page 1-5. IEEE, (2019)Ower and Area Efficient Router with Automated Clock Gating for Neuromorphic Computing., , , , and . SoCC, page 27-32. IEEE, (2019)3881 Gbps/W, 3005 µm AES Core with State Based Clock Gating for IoT applications., , , , and . ISCAS, page 1-5. IEEE, (2024)Coverage Driven Verification Methodology for Asynchronous Neuromorphic Routers., , , , and . SoCC, page 242-247. IEEE, (2019)A 1800μm2, 953Gbps/W AES Accelerator for IoT Applications in 40nm CMOS., , , , , , and . ISCAS, page 2433-2437. IEEE, (2022)Exploring Error Correction Circuits on RISC-V based Systems for Space Applications., , , and . ISCAS, page 1-5. IEEE, (2024)A real-time near infrared image acquisition system based on image quality assessment., , , and . J. Real-Time Image Processing, 13 (1): 103-120 (2017)Co-simulation methodology for improved design and verification of hardware neural networks., , and . IECON, page 2226-2231. IEEE, (2013)0.08mm2 128nW MFCC Engine for Ultra-low Power, Always-on Smart Sensing Applications., , , , and . ISCAS, page 2680-2684. IEEE, (2022)