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Disambiguation of "Kim, Chris H."

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A logic-compatible embedded flash memory featuring a multi-story high voltage switch and a selective refresh scheme.

, , and . VLSIC, page 130-131. IEEE, (2012)

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Nam-h Kim

Nam-h Kim

Chris H J F Eigkemans

Ki-h ng Kim

Ch ng-h Kim

 

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A Probabilistic Compute Fabric Based on Coupled Ring Oscillators for Solving Combinatorial Optimization Problems., , , and . IEEE J. Solid State Circuits, 56 (9): 2870-2880 (2021)A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital Equalizer., , , and . A-SSCC, page 187-190. IEEE, (2018)A multi-story power delivery technique for 3D integrated circuits., , , and . ISLPED, page 57-62. ACM, (2008)19.2 A 0.2-to-1.45GHz subsampling fractional-N all-digital MDLL with zero-offset aperture PD-based spur cancellation and in-situ timing mismatch detection., , and . ISSCC, page 326-327. IEEE, (2016)A fully integrated 40pF output capacitor beat-frequency-quantizer-based digital LDO with built-in adaptive sampling and active voltage positioning., , , , and . ISSCC, page 308-310. IEEE, (2018)A 0.4-1.6GHz spur-free bang-bang digital PLL in 65nm with a D-flip-flop based frequency subtractor circuit., , and . VLSIC, page 140-. IEEE, (2015)A multi-phase VCO quantizer based adaptive digital LDO in 65nm CMOS technology., and . ISCAS, page 1-4. IEEE, (2017)A Counter based ADC Non-linearity Measurement Circuit and Its Application to Reliability Testing., , , , , and . CICC, page 1-4. IEEE, (2019)SRAM read performance degradation under asymmetric NBTI and PBTI stress: Characterization vehicle and statistical aging data., , and . CICC, page 1-4. IEEE, (2014)Sleep Transistor Sizing and Adaptive Control for Supply Noise Minimization Considering Resonance., , , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (9): 1203-1211 (2009)