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NoSQ: Store-Load Communication without a Store Queue., , and . MICRO, page 285-296. IEEE Computer Society, (2006)Token tenure: PATCHing token counting using directory-based cache coherence., , and . MICRO, page 47-58. IEEE Computer Society, (2008)Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared-Memory Multiprocessors., , , , and . ISCA, page 206-217. IEEE Computer Society, (2003)InvisiFence: performance-transparent memory ordering in conventional multiprocessors., , and . ISCA, page 233-244. ACM, (2009)WatchdogLite: Hardware-Accelerated Compiler-Based Pointer Checking., , and . CGO, page 175. ACM, (2014)Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset., , , , , , , , and . SIGARCH Comput. Archit. News, 33 (4): 92-99 (2005)Subtleties of Transactional Memory Atomicity Semantics., , and . IEEE Comput. Archit. Lett., (2006)An Axiomatic Memory Model for POWER Multiprocessors., , , , , , , , , and . CAV, volume 7358 of Lecture Notes in Computer Science, page 495-512. Springer, (2012)Scalable Store-Load Forwarding via Store Queue Index Prediction., , and . MICRO, page 159-170. IEEE Computer Society, (2005)Exploiting Dead Value Information., , and . MICRO, page 125-135. ACM/IEEE Computer Society, (1997)