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Disambiguation of "Calazans, Ney Laert Vilar"

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Prototyping of embedded digital systems from SDL language: a case study.

, , , , , and . HLDVT, page 133-138. IEEE Computer Society, (2002)

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Loreto Vilar

Ignazio Vilardi

Fabio Vilardi

Sisi Alexandra Vilardi

David Vilar Torres

 

Other publications of authors with the same name

Design and analysis of the HF-RISC processor targeting voltage scaling applications., , , , , , and . SBCCI, page 1-6. IEEE, (2016)Automated Synthesis of Cell Libraries for Asynchronous Circuits., , , , and . SBCCI, page 16:1-16:7. ACM, (2014)Evaluating the robustness of secure triple track logic through prototyping., , , , , and . SBCCI, page 193-198. ACM, (2008)Go functional model for a RISC-V asynchronous organisation - ARV., and . ICECS, page 381-384. IEEE, (2017)Design and Analysis of Testable Mutual Exclusion Elements., , , , , , and . ASYNC, page 124-131. IEEE Computer Society, (2015)Blade - A Timing Violation Resilient Asynchronous Template., , , , , , , , , and . ASYNC, page 21-28. IEEE Computer Society, (2015)Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications., , , , , and . ASYNC, page 11-18. IEEE Computer Society, (2016)Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codes., , and . SBCCI, page 1-6. IEEE, (2012)A design flow for physical synthesis of digital cells with ASTRAN., , , , and . ACM Great Lakes Symposium on VLSI, page 245-246. ACM, (2014)Rate-based scheduling policy for QoS flows in networks on chip., and . VLSI-SoC, page 140-145. IEEE, (2007)