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19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC., , , , , , , и . ISSCC, стр. 324-325. IEEE, (2016)A 2.7 GHz to 7 GHz Fractional-N LC-PLL Utilizing Multi-Metal Layer SoC Technology in 28 nm CMOS., , , , , , и . IEEE J. Solid State Circuits, 50 (4): 856-866 (2015)F4: Emerging short-reach and high-density interconnect solutions for internet of everything., , , , , и . ISSCC, стр. 502-505. IEEE, (2016)F1: High-speed interleaved ADCs., , , и . ISSCC, стр. 1-2. IEEE, (2015)8.6 A full-duplex line driver for Gigabit Ethernet with rail-to-rail class-AB output stage in 28nm CMOS., , , , , , , , , и 1 other автор(ы). ISSCC, стр. 148-149. IEEE, (2014)A 2.7GHz to 7GHz fractional-N LCPLL utilizing multimetal layer SoC technology in 28nm CMOS., , , , , , и . VLSIC, стр. 1-2. IEEE, (2014)10.3 An analog front-end for 100BASE-T1 automotive Ethernet in 28nm CMOS., , , , , , , , , и 9 other автор(ы). ISSCC, стр. 186-187. IEEE, (2016)Session 7 overview: Optical transceivers and silicon photonics., и . ISSCC, стр. 114-115. IEEE, (2013)A fully integrated SONET OC-48 transceiver in standard CMOS., , , , , , , , , и 1 other автор(ы). IEEE J. Solid State Circuits, 36 (12): 1964-1973 (2001)F5: Wireline transceivers for Mega Data Centers: 50Gb/s and beyond., , , , , и . ISSCC, стр. 512-514. IEEE, (2017)