Author of the publication

A single bit 6.8mW 10MHz power-optimized continuous-time ΔΣ with 67dB DR in 90nm CMOS.

, , , and . ESSCIRC, page 336-339. IEEE, (2009)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Massively multi-topology sizing of analog integrated circuits., , , and . DATE, page 706-711. IEEE, (2009)Design of high-speed analog-to-digital interface in digital technologies., and . ICECS, page 493-496. IEEE, (2001)SFDR-bandwidth limitations for high speed high resolution current steering CMOS D/A converters., , and . ICECS, page 1193-1196. IEEE, (1999)RFID, where are they?, , , , , , , , , and 2 other author(s). ESSCIRC, page 36-43. IEEE, (2009)Power efficient 4.5Gbit/s optical receiver in 130nm CMOS with integrated photodiode., and . ESSCIRC, page 162-165. IEEE, (2008)EMI resisting voltage regulator with large signal PSR up to 1GHz., and . ESSCIRC, page 391-394. IEEE, (2013)A 120GHz fully integrated 10Gb/s wireless transmitter with on-chip antenna in 45nm low power CMOS., , , , , and . ESSCIRC, page 331-334. IEEE, (2013)Oscillator pulling and synchronisation issues in self-oscillating class D power amplifiers., and . ESSCIRC, page 529-532. IEEE, (2003)Dynamic biasing: a low power linearisation technique., and . ESSCIRC, page 369-372. IEEE, (2003)Three stage amplifier frequency compensation., , , and . ESSCIRC, page 365-368. IEEE, (2003)