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Architecture-level power estimation and design experiments.

, , and . ACM Trans. Design Autom. Electr. Syst., 6 (1): 50-66 (2001)

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Exploiting communication complexity for multilevel logic synthesis., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 9 (10): 1017-1027 (1990)Efficiently computing communication complexity for multilevel logic synthesis., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 11 (5): 545-554 (1992)A hybrid NoC design for cache coherence optimization for chip multiprocessors., , , , , and . DAC, page 834-842. ACM, (2012)Secretary/Treasurer's Report.. SIGARCH Comput. Archit. News, 14 (4): 28 (1986)Number representations for reducing switched capacitance in subband coding., and . ICASSP, page 3125-3128. IEEE, (1998)Managing Leakage Energy in Cache Hierarchies., , , , , , and . J. Instruction-Level Parallelism, (2003)On the Effects of Process Variation in Network-on-Chip Architectures., , , , , , and . IEEE Trans. Dependable Secur. Comput., 7 (3): 240-254 (2010)Reduction of broadband noise in speech by spectral weighting.. ICASSP, page 1045-1051. IEEE, (1980)Accurate Estimation of Combinational Circuit Activity., , , and . DAC, page 618-622. ACM Press, (1995)Validation of an Architectural Level Power Analysis Technique., , , and . DAC, page 242-245. ACM Press, (1998)