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A 10 Gbps in-line network security processor based on configurable hetero-multi-cores.

, , , , and . Journal of Zhejiang University - Science C, 14 (8): 642-651 (2013)

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A 10Gbps in-line Network Security Processor with a 32-bit embedded CPU., , , , and . WOCC, page 616-619. IEEE, (2013)New power rail ESD clamp design with current starving technology., , and . ASICON, page 961-964. IEEE, (2011)Reflection analysis of signal transmission in 32-bit CPU based SiP., , and . ASICON, page 743-746. IEEE, (2011)Design and implementation of a low Power Java Coprocessor for dual-interface IC Bank Card., , and . ASICON, page 965-969. IEEE, (2011)A 10 Gbps in-line network security processor based on configurable hetero-multi-cores., , , , and . Journal of Zhejiang University - Science C, 14 (8): 642-651 (2013)A novel ESD device for Whole-Chip ESD protection network of TPMS mixed signal SoC., , , , and . ASICON, page 1-4. IEEE, (2013)Examination of relevance criteria choices and the information search process, , and . Journal of Documentation, 65 (5): 719--744 (2009)Testing visualization on the use of information systems., , and . IIiX, page 365-370. ACM, (2010)Research on Temperature Characteristics of IoT Chip Hardware Trojan Based on FPGA., , , , and . CSPS, volume 571 of Lecture Notes in Electrical Engineering, page 1222-1230. Springer, (2019)An Improved Cross-Coupled NAND Gates PUF for Bank IC Card., , , and . ICCSP, page 150-153. ACM, (2018)