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LV*: A low complexity lazy versioning HTM infrastructure.

, , и . ICSAMOS, стр. 231-240. IEEE, (2010)

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Devender Singh Negi

Anurag Gupta

Anurag Anand

Anurag Mishra

Anurag Dave

 

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Performance and Energy Analysis of the Restricted Transactional Memory Implementation on Haswell., , , , и . IPDPS, стр. 615-624. IEEE Computer Society, (2014)SCIN-cache: Fast speculative versioning in multithreaded cores., и . ACM Trans. Archit. Code Optim., 9 (4): 58:1-58:26 (2013)π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory., , , , и . HPCA, стр. 141-152. IEEE Computer Society, (2012)Techniques to improve performance in requester-wins hardware transactional memory., , , , и . ACM Trans. Archit. Code Optim., 10 (4): 42:1-42:25 (2013)LV*: a class of lazy versioning HTMs for low-cost integration of transactional memory systems., , и . IFMT, стр. 5:1-5:10. ACM, (2010)The Impact of Non-coherent Buffers on Lazy Hardware Transactional Memory Systems., , , , и . IPDPS Workshops, стр. 700-707. IEEE, (2011)Eager Beats Lazy: Improving Store Management in Eager Hardware Transactional Memory., , , , и . IEEE Trans. Parallel Distributed Syst., 24 (11): 2192-2201 (2013)HARP: Adaptive abort recurrence prediction for Hardware Transactional Memory., , , , , и . HiPC, стр. 196-205. IEEE Computer Society, (2013)Transactional prefetching: narrowing the window of contention in hardware transactional memory., , , , и . PACT, стр. 181-190. ACM, (2012)Eager Meets Lazy: The Impact of Write-Buffering on Hardware Transactional Memory., , , , и . ICPP, стр. 73-82. IEEE Computer Society, (2011)