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Disambiguation of "Díaz-Madrid, José Ángel"

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Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing.

, , , , and . DATE, page 369-373. IEEE, (2009)

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José Díaz Basto

David José Martínez Díaz

José Ángel Santamaría Araújo

José Alonso Enríquez Díaz

José Ignacio Gutiérrez Díaz

 

Other publications of authors with the same name

An 11-bit 20-MSample/s pipelined ADC with OTA bias current regulation to optimize power dissipation., , , and . ISCAS, page 1-4. IEEE, (2017)Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing., , , , and . DATE, page 369-373. IEEE, (2009)Improvement of ANNs Performance to Generate Fitting Surfaces for Analog CMOS Circuits., , , , and . IWINAC (2), volume 4528 of Lecture Notes in Computer Science, page 19-27. Springer, (2007)A 12T SRAM in-Memory Computing differential current architecture for CNN implementations., , , and . ISCAS, page 1-5. IEEE, (2023)Accurate and reusable macromodeling technique using a fuzzy-logic approach., , , and . ISCAS, page 508-511. IEEE, (2008)An all-hardware implementation of the subpixel refinement stage in SIFT algorithm., , , , , , and . Int. J. Circuit Theory Appl., 46 (9): 1690-1702 (2018)An Analogue Current-Mode Hardware Design Proposal for Preprocessing Layers in ART-Based Neural Networks., , , and . IWANN (2), volume 2687 of Lecture Notes in Computer Science, page 97-104. Springer, (2003)Current Mode CMOS Synthesis of a Motor-Control Neural System., , , and . IWANN (2), volume 2687 of Lecture Notes in Computer Science, page 25-32. Springer, (2003)Fuzzy logic technique for accurate analog circuits macromodel sizing., , and . I. J. Circuit Theory and Applications, 38 (3): 307-319 (2010)All-hardware SIFT implementation for real-time VGA images feature extraction., , , , , , and . J. Real Time Image Process., 17 (2): 371-382 (2020)