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Disambiguation of "Fujino, Takeshi"

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A Low Power Embedded DRAM Macro for Battery-Operated LSIs.

, , , , , , , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 86-A (12): 2991-3000 (2003)

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Takeshi Morita

Hiroshi Fujino

Takeshi Morita

Takeshi Imamura

Takeshi Omori

 

Other publications of authors with the same name

Adversarial Scan Attack against Scan Matching Algorithm for Pose Estimation in LiDAR-Based SLAM., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 105-A (3): 326-335 (2022)Deep Learning Side-Channel Attacks Against Lightweight SCA Countermeasure RSM-AES., , , and . AsianHOST, page 1-6. IEEE, (2021)On Measurable Side-Channel Leaks Inside ASIC Design Primitives., , , , and . CHES, volume 8086 of Lecture Notes in Computer Science, page 159-178. Springer, (2013)Area-Efficient Post-Processing Circuits for Physically Unclonable Function with 2-Mpixel CMOS Image Sensor., , , , , , and . Sensors, 21 (18): 6079 (2021)Hybrid masking using intra-masking dual-rail memory on LUT for SCA-Resistant AES implementation on FPGA (abstract only)., and . FPGA, page 266-267. ACM, (2013)FPGA Implementation of Physically Unclonable Functions Based on Multi-threshold Delay Time Measurement Method to Mitigate Modeling Attacks., , , , and . ACNS Workshops (1), volume 14586 of Lecture Notes in Computer Science, page 65-83. Springer, (2024)Intra-masking dual-rail memory on LUT implementation for tamper-resistant AES on FPGA., and . FPGA, page 1-10. ACM, (2012)Interleaved-bitslice AES encryption and decryption with massive-parallel mobile embedded processor., , and . APCCAS, page 359-362. IEEE, (2014)A Dynamic Soft-Decision Fuzzy Extractor for a CMOS Image Sensor PUF., , , , , , , and . ISPACS, page 54-59. IEEE, (2018)Hierarchical image-scrambling method with scramble-level controllability for privacy protection., , , , and . MWSCAS, page 1371-1374. IEEE, (2013)