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Design of a radix-2m hybrid array multiplier using carry save adder format.

, , , and . SBCCI, page 172-177. ACM, (2005)

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Floating-point adaptive filter architectures for the cancelling of harmonics power line interference., , , and . ICECS, page 609-612. IEEE, (2015)Design of a radix-2m hybrid array multiplier using carry save adder format., , , and . SBCCI, page 172-177. ACM, (2005)Exploiting adder compressors for power-efficient 2-D approximate DCT realization., , , , and . LASCAS, page 383-386. IEEE, (2016)Design of optimized radix-2 and radix-4 butterflies from FFT with decimation in time., , and . LASCAS, page 171-174. IEEE, (2016)A power-efficient 4-2 Adder Compressor topology., , , , , and . NEWCAS, page 281-284. IEEE, (2017)Optimal combination of dedicated multiplication blocks and adder trees schemes for optimized radix-2m array multipliers realization., , and . ICECS, page 352-355. IEEE, (2015)Power efficient 2-D rounded cosine transform with adder compressors for image compression., , , and . ICECS, page 348-351. IEEE, (2015)SATD hardware architecture based on 8×8 Hadamard Transform for HEVC encoder., , , and . ICECS, page 576-579. IEEE, (2015)Modeling and Evaluating Personas with Software Explainability Requirements., , and . HCI-COLLAB, volume 1478 of Communications in Computer and Information Science, page 136-149. Springer, (2021)Exploiting architectural solutions for IIR filter architecture with truncation error feedback., , , and . LASCAS, page 375-378. IEEE, (2016)