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Disambiguation of "Reddy, Sudhakar M."

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Accurate Diagnosis of Interconnect Open Defects Based on the Robust Enhanced Aggressor Victim Model.

, , , and . VLSI Design, page 135-140. IEEE Computer Society, (2017)

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Sudhakar Peddireddi

Padhmanand Sudhakar

Edamakanti Chandrakanth Reddy

Malgi Prasad Reddy

Martin Reddy

 

Other publications of authors with the same name

Worst-case and average-case analysis of n-detection test sets and test generation strategies., and . IET Comput. Digit. Tech., 1 (4): 353-363 (2007)Diagnosis of path delay faults based on low-coverage tests., and . IET Comput. Digit. Tech., 4 (2): 89-103 (2010)Functional Broadside Tests Under an Expanded Definition of Functional Operation Conditions., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (1): 121-129 (2009)Forward-Looking Reverse Order Fault Simulation for n -Detection Test Sets., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (9): 1424-1428 (2009)TOV: Sequential Test Generation by Ordering of Test Vectors., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (3): 454-465 (2010)Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (2): 398-403 (2008)On synchronizable circuits and their synchronizing sequences., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (9): 1086-1092 (2000)Theorems for identifying undetectable faults in partial-scan circuits., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (8): 1092-1097 (2003)Test compaction for at-speed testing of scan circuits based onnonscan test. sequences and removal of transfer sequences., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (6): 706-714 (2002)Techniques for minimizing power dissipation in scan and combinational circuits during test application., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 17 (12): 1325-1333 (1998)