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FPGA implementation of reconfigurable ADPLL network for distributed clock generation.

C. Shan, E. Zianbetov, M. Javidan, F. Anceau, M. Terosiet, S. Feruglio, D. Galayko, O. Romain, É. Colinet, and J. Juillard. FPT, page 1-4. IEEE, (2011)

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Dimitri Barski

Dimitri Hartl

Dimitri Chronopulos

Thomas Dimitri

Dimitri Emeljanenko

Other publications of authors with the same name

Autonomous CMOS Power Management Integrated Circuit for Electrostatic Kinetic Energy Harvesters e-KEH.A. Bessaad, A. Rhouni, P. Basset, and D. Galayko. ICECS, page 338-341. IEEE, (2019)A CMOS inductor-less PMIC with MPPT and burst control for a 600 μW magnetoelectric transducer.J. Sánchez-Chiva, D. Galayko, and A. Rhouni. ISCAS, page 1882-1886. IEEE, (2022)Control law synthesis for distributed multi-agent systems: Application to active clock distribution networks.A. Korniienko, G. Scorletti, É. Colinet, E. Blanco, J. Juillard, and D. Galayko. ACC, page 4691-4696. IEEE, (2011)All-Digital Phase-Locked Loop Arrays: Investigation of Synchronisation and Jitter Performance through FPGA Prototyping.E. Koskin, P. Bisiaux, D. Galayko, and E. Blokhina. NEWCAS, page 1-4. IEEE, (2019)Electromechanical coupling in electrostatic kinetic energy harvesters.E. O'Riordan, E. Blokhina, and D. Galayko. ICECS, page 436-437. IEEE, (2016)SystemC-AMS Modeling of an Electromechanical Harvester of Vibration Energy.K. Caluwaerts, and D. Galayko. FDL, page 99-104. IEEE, (2008)SystemC-AMS Heterogeneous Modeling of a Capacitive Harvester of Vibration Energy.K. Caluwaerts, D. Galayko, and P. Basset. BMAS, page 142-147. IEEE, (2008)Nonlinearities in electrostatic vibration energy harvesters: A review using the example of a charge pump conditioning circuit.E. Blokhina, E. O'Riordan, O. Feely, and D. Galayko. ISCAS, page 2604-2607. IEEE, (2014)Electrostatic vibration energy harvester with piezoelectric start-up generator.H. Florentino, R. Freire, A. Sà, C. Florentino, and D. Galayko. ISCAS, page 1343-1346. IEEE, (2011)Open Source Hardware and EDA Tools for Analog/Mixed-Signal Design and Prototyping.N. Shimizu, J. Akita, M. Louërat, H. Stratigopoulos, J. Chaput, and D. Galayko. ISCAS, page 1-5. IEEE, (2018)

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Disambiguation of "Galayko, Dimitri"

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FPGA implementation of reconfigurable ADPLL network for distributed clock generation.

Please choose a person to relate this publication to

Dimitri Barski

Dimitri Hartl

Dimitri Chronopulos

Thomas Dimitri

Dimitri Emeljanenko

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Galayko, Dimitri"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML FPGA implementation of reconfigurable ADPLL network for distributed clock generation.

Please choose a person to relate this publication to

Dimitri Barski

Dimitri Hartl

Dimitri Chronopulos

Thomas Dimitri

Dimitri Emeljanenko

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

FPGA implementation of reconfigurable ADPLL network for distributed clock generation.