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Disambiguation of "Shanbhag, Naresh R."

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An Energy-Efficient Programmable Mixed-Signal Accelerator for Machine Learning Algorithms.

, , , , and . IEEE Micro, 39 (5): 64-72 (2019)

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Naresh Yallapragada

Uma-Naresh Niranjan

Naresh Bikash Dasgupta

Naresh Reddy Thumati

Naresh Chandra Varshneya

 

Other publications of authors with the same name

A Variation-Tolerant In-Memory Machine Learning Classifier via On-Chip Training., , and . IEEE J. Solid State Circuits, 53 (11): 3163-3173 (2018)Analytical estimation of signal transition activity from word-level statistics., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (7): 718-733 (1997)Area-efficient high-throughput MAP decoder architectures., , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (8): 921-933 (2005)A voltage overscaled low-power digital filter IC., and . IEEE J. Solid State Circuits, 39 (2): 388-391 (2004)Low-power reconfigurable signal processing via dynamic algorithm transformations (DAT)., and . ICASSP, page 3081-3084. IEEE, (1998)A low-power bus design using joint repeater insertion and coding., and . ISLPED, page 99-102. ACM, (2005)Low-power AEC-based MIMO signal processing for gigabit ethernet 1000Base-T transceivers., and . ISLPED, page 334-339. ACM, (2001)An energy-efficient memory-based high-throughput VLSI architecture for convolutional networks., , , and . ICASSP, page 1037-1041. IEEE, (2015)Design methodology for high-speed iterative decoder architectures., and . ICASSP, page 3085-3088. IEEE, (2002)A 19.4 nJ/decision 364K decisions/s in-memory random forest classifier in 6T SRAM array., , and . ESSCIRC, page 263-266. IEEE, (2017)