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The Impact of Page Size and Microarchitecture on Instruction Address Translation Overhead., , , and . ACM Trans. Archit. Code Optim., 20 (3): 38:1-38:25 (September 2023)Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power., , , , , , , and . IEEE PACT, page 141-152. IEEE Computer Society, (2002)Performance Characterization of HTAP Workloads., , and . ICDE, page 1829-1834. IEEE, (2021)Reducing the complexity of the register file in dynamic superscalar processors., , and . MICRO, page 237-248. ACM/IEEE Computer Society, (2001)Software Versus Hardware Shared-Memory Implementation: A Case Study., , , , , and . ISCA, page 106-117. IEEE Computer Society, (1994)Dynamically allocating processor resources between nearby and distant ILP., , and . ISCA, page 26-37. ACM, (2001)Towards practical page coloring-based multicore cache management., , and . EuroSys, page 89-102. ACM, (2009)Shielding Software From Privileged Side-Channel Attacks., , , , and . USENIX Security Symposium, page 1441-1458. USENIX Association, (2018)Software Distributed Shared Memory.. Encyclopedia of Parallel Computing, Springer, (2011)TreadMarks: Distributed Shared Memory on Standard Workstations and Operating Systems., , , and . USENIX Winter, page 115-132. USENIX Association, (1994)