( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Algorithms for Generating Ordered Solutions for Explicit AND/OR Structures.

, , , и . CoRR, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

P Günther

P Kock

P Krebietke

P Hümmer

-P Schwarz

 

Другие публикации лиц с тем же именем

Pruning by Upperbounds in Heuristic Search: Use of Approximate Algorithms., , , и . KBCS, том 444 из Lecture Notes in Computer Science, стр. 451-461. Springer, (1989)Safe-ERfair., , , и . VLSI Design, стр. 128-133. IEEE Computer Society, (2010)Dictionary Based Code Compression for Variable Length Instruction Encodings., , и . VLSI Design, стр. 545-550. IEEE Computer Society, (2005)A Hierarchical Cost Tree Mutation Approach to Optimization of Analog Circuits., , и . VLSI Design, стр. 535-538. IEEE Computer Society, (2005)Syntactic Transformation of Assume-Guarantee Assertions: From Sub-Modules to Modules., , и . VLSI Design, стр. 213-218. IEEE Computer Society, (2005)Design Space Exploration for Data Path Synthesis., , и . VLSI Design, стр. 166-173. IEEE Computer Society, (1997)Timing Verification of UML Activity Diagram Based Code Block Level Models for Real Time Multiprocessor System-on-Chip Applications., , и . APSEC, стр. 199-208. IEEE Computer Society, (2006)Finding Critical Components in Embedded Control Systems Sensitive to Quality-Faults., , , , и . ISED, стр. 167-171. IEEE, (2012)AWA* - A Window Constrained Anytime Heuristic Search Algorithm., , и . IJCAI, стр. 2250-2255. (2007)Timing analysis of tree-like RLC circuits., , , , , и . ISCAS (4), стр. 838-841. IEEE, (2002)