Author of the publication

Work-in-Progress: A Flexible Router Architecture for 3D NoCs.

, , and . RTSS, page 375-377. IEEE Computer Society, (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A reusable verification environment for NoC platforms using UVM., , , , , , , and . EUROCON, page 239-242. IEEE, (2017)RVNoC: A Framework for Generating RISC-V NoC-Based MPSoC., , , , , , , and . PDP, page 617-621. IEEE Computer Society, (2018)A Configurable RISC-V for NoC-Based MPSoCs: A Framework for Hardware Emulation., , , , and . NoCArc@MICRO, page 1-6. IEEE Computer Society, (2018)Evaluating the feasibility of centralized router for network on chip., , and . ICM, page 238-241. IEEE, (2015)A novel power reduction technique using wire multiplexing., , , and . SoCC, page 149-152. IEEE, (2017)A 4-PAM interconnect in network-on-chip for high-throughput and latency-sensitive applications., , , , and . ISQED, page 112-118. IEEE, (2018)On Error Injection for NoC Platforms: A UVM-based Practical Case Study., , , , , , and . NoCArc@MICRO, page 2:1-2:6. ACM, (2017)A novel assertions-based code coverage automatic CAD tool., , , and . EUROCON, page 277-281. IEEE, (2017)Emulation and verification framework for MPSoC based on NoC and RISC-V., , , , and . Des. Autom. Embed. Syst., 26 (3): 133-159 (December 2022)A narrative of UVM testbench environment for interconnection routers: A practical approach., , , , , , , and . IDT, page 98-103. IEEE, (2016)