( en | de | ru )

 

Disambiguation of "Shafaei, Alireza"

Author of the publication

copydeleteadd this publication to your clipboard
A thermally-aware energy minimization methodology for global interconnects.

, , , and . DATE, page 1213-1218. IEEE, (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Mohsen Shafaei

Shahram Shafaei

Alireza Azem

Alireza Mirshahi

Alireza Djirsarai

 

Other publications of authors with the same name

A 125mV 2ns-access-time 16Kb SRAM design based on a 6T hybrid TFET-FinFET cell., , and . ISQED, page 280-285. IEEE, (2018)MASAGA: A Linearly-Convergent Stochastic First-Order Method for Optimization on Manifolds., , , and . ECML/PKDD (2), volume 11052 of Lecture Notes in Computer Science, page 344-359. Springer, (2018)Unlabelled 3D Motion Examples Improve Cross-View Action Recognition., , , and . BMVC, BMVA Press, (2014)Reversible logic synthesis of k-input, m-output lookup tables., , and . DATE, page 1235-1240. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Optimizing the Operating Voltage of Tunnel FET-Based SRAM Arrays Equipped with Read/Write Assist Circuitry., , and . ACM Great Lakes Symposium on VLSI, page 415-420. ACM, (2016)A Less Biased Evaluation of Out-of-distribution Sample Detectors., , and . BMVC, page 3. BMVA Press, (2019)Low write-energy STT-MRAMs using FinFET-based access transistors., , and . ICCD, page 374-379. IEEE Computer Society, (2014)Minimizing the energy-delay product of SRAM arrays using a device-circuit-architecture co-optimization framework., , and . DAC, page 107:1-107:6. ACM, (2016)Design of a universal logic block for fault-tolerant realization of any logic operation in trapped-ion quantum circuits., , , and . Quantum Inf. Process., 13 (5): 1267-1299 (2014)A thermally-aware energy minimization methodology for global interconnects., , , and . DATE, page 1213-1218. IEEE, (2017)