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Disambiguation of "Raghunathan, Anand"

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Ax-BxP: Approximate Blocked Computation for Precision-reconfigurable Deep Neural Network Acceleration.

, , and . ACM Trans. Design Autom. Electr. Syst., 27 (3): 28:1-28:20 (2022)

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Davinder Kumar Anand

Raghunathan Ramakrishnan

Devanathan Raghunathan

Amar Frank Anand

Madhankumar Anandhakrishnan

 

Other publications of authors with the same name

Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips., , , and . DAC, page 513-518. ACM, (2000)Analyzing the energy consumption of security protocols., , , and . ISLPED, page 30-35. ACM, (2003)System-on-Chip Power Management Considering Leakage Power Variations., , , and . DAC, page 877-882. IEEE, (2007)High-level energy macromodeling of embedded software., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (9): 1037-1050 (2002)Application-specific heterogeneous multiprocessor synthesis using extensible processors., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (9): 1589-1602 (2006)Generation of distributed logic-memory architectures through high-level synthesis., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (11): 1694-1711 (2005)Pack and Detect: Fast Object Detection in Videos Using Region-of-Interest Packing., , and . COMAD/CODS, page 150-156. ACM, (2019)High-Level Synthesis with SIMD Units., , , and . ASP-DAC/VLSI Design, page 407-413. IEEE Computer Society, (2002)Coping with Variations through System-Level Design., , , , , and . VLSI Design, page 581-586. IEEE Computer Society, (2009)Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip., , , , and . VLSI Design, page 65-70. IEEE Computer Society, (2005)