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On-Chip Interconnection Networks of the TRIPS Chip., , , , , , and . IEEE Micro, 27 (5): 41-50 (2007)A Neuroevolution Method for Dynamic Resource Allocation on a Chip Multiprocessor, , and . Proceedings of the INNS-IEEE International Joint Conference on Neural Networks, page 2355--2361. Piscataway, NJ, IEEE, (2001)Memory Systems., , and . The Computer Science and Engineering Handbook, CRC Press, (1997)Microprocessor pipeline energy analysis., , , , and . ISLPED, page 282-287. ACM, (2003)Register Bank Assignment for Spatially Partitioned Processors., , , and . LCPC, volume 5335 of Lecture Notes in Computer Science, page 64-79. Springer, (2008)Billion-Transistor Architectures - Guest Editors' Introduction., and . Computer, 30 (9): 46-49 (1997)Multicore Model from Abstract Single Core Inputs., , , , and . IEEE Comput. Archit. Lett., 12 (2): 59-62 (2013)Scalable Hardware Memory Disambiguation for High ILP Processors., , , , and . MICRO, page 399-410. IEEE Computer Society, (2003)Dataflow Predication., , , , , , and . MICRO, page 89-102. IEEE Computer Society, (2006)Distributed Microarchitectural Protocols in the TRIPS Prototype Processor., , , , , , , , , and 7 other author(s). MICRO, page 480-491. IEEE Computer Society, (2006)