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VLSI implementation of an area-efficient architecture for the Viterbi algorithm.

, , and . ICASSP, page 623-626. IEEE Computer Society, (1997)

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Algorithms and Hardware for Data Compression in Point Rendering Applications., , , and . WSCG (Short Papers), page 173-180. (2004)High performance VLSI architecture for the trellis coded quantization., , , and . ICIP (2), page 995-998. IEEE Computer Society, (1996)Parallel hierarchical radiosity on hybrid platforms., , , , and . J. Supercomput., 58 (3): 357-366 (2011)A new architecture for efficient hybrid representation of terrains., and . J. Syst. Archit., 54 (1-2): 145-160 (2008)High-performance Monte Carlo radiosity on GPU based on scene partitioning., , , and . Microprocess. Microsystems, 36 (2): 88-95 (2012)Concentric Strips: Algorithms and Architecture for the Compression/Decompression of Triangle Meshes., , , and . 3DPVT, page 380-383. IEEE Computer Society, (2002)Arithmetic Image Coding/Decoding Architecture Based on a Cache Memory., , and . EUROMICRO, page 10139-. IEEE Computer Society, (1998)Mapping of Trellises Associated with General Encoders onto High-Performance VLSI Architectures., , , and . VLSI Signal Processing, 17 (1): 57-73 (1997)Hybrid Terrain Visualization based on Local Tessellations., , , and . GRAPP, page 64-69. INSTICC Press, (2009)Adaptive Tessellation of NURBS Surfaces., , , and . WSCG, (2003)