( en | de | ru )

 

Disambiguation of "Jafri, Syed M. A. H."

Author of the publication

copydeleteadd this publication to your clipboard
NeuroCGRA: A CGRA with support for neural networks.

, , , , , , and . HPCS, page 506-511. IEEE, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

A H M Belayeth Hussain

A H M Belayeth Hussain

Wafaa M H A Zidan

A M Otto

Rabia Jafri

 

Other publications of authors with the same name

Exploring Spiking Neural Network on Coarse-Grain Reconfigurable Architectures., , , , , , , , and . MES, page 64-67. ACM, (2014)RuRot: Run-time rotatable-expandable partitions for efficient mapping in CGRAs., , , , , , , and . ICSAMOS, page 233-241. IEEE, (2014)Compression Based Efficient and Agile Configuration Mechanism for Coarse Grained Reconfigurable Architectures., , , , and . IPDPS Workshops, page 290-293. IEEE, (2011)Implementation and evaluation of configuration scrubbing on CGRAs: A case study., , , , , and . ISSoC, page 1-8. IEEE, (2013)NeuroCGRA: A CGRA with support for neural networks., , , , , , and . HPCS, page 506-511. IEEE, (2014)Parallel distributed scalable runtime address generation scheme for a coarse grain reconfigurable computation and storage fabric., , , , , and . Microprocess. Microsystems, 38 (8): 788-802 (2014)Can a reconfigurable architecture beat ASIC as a CNN accelerator?, , and . SAMOS, page 97-104. IEEE, (2017)Clock Tree Generation by Abutment in Synchoros VLSI Design., , , and . NorCAS, page 1-7. IEEE, (2021)MTP-Caffe: Memory, Timing, and Power aware tool for mapping CNNs to GPUs., , , and . PARMA-DITAM@HiPEAC, page 31-36. ACM, (2017)Compact generic intermediate representation (CGIR) to enable late binding in coarse grained reconfigurable architectures., , , , and . FPT, page 1-6. IEEE, (2011)