( en | de | ru )

 

Disambiguation of "Davidson, Edward S."

Author of the publication

copydeleteadd this publication to your clipboard
Register Queues: A New Hardware/Software Approach to Efficient Software Pipelining.

, , and . IEEE PACT, page 3-12. IEEE Computer Society, (2000)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Georg Davidson

Marianne Davidson

Anika Davidson

Fordyce Davidson

G Davidson

 

Other publications of authors with the same name

Author retrospective for optimum modulo schedules for minimum register requirements., , and . ICS 25th Anniversary, page 35-36. ACM, (2014)An evaluation of Cray X-MP performance on vectorizable Livermore FORTRAN kernels., and . ICS, page 510-518. ACM, (1988)Maximum rate single-phase clocking of a closed pipeline including wave pipelining, stoppability, and startability., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (12): 1526-1545 (1995)An integrated approach to developing manufacturing control software., , and . ICRA, page 1979-1984. IEEE Computer Society, (1991)Register Queues: A New Hardware/Software Approach to Efficient Software Pipelining., , and . IEEE PACT, page 3-12. IEEE Computer Society, (2000)A custom-designed integrated circuit for the realization of residue number digital filters., , and . ICASSP, page 220-223. IEEE, (1985)Evaluating database management systems.. AFIPS National Computer Conference, volume 51 of AFIPS Conference Proceedings, page 639-648. AFIPS Press, (1982)A Prefetch Taxonomy., , and . IEEE Trans. Computers, 53 (2): 126-140 (2004)Probabilistic Predicate-Aware Modulo Scheduling., , and . CGO, page 151-162. IEEE Computer Society, (2004)Performance of Shared Cache for Parallel-Pipelined Computer Systems, , and . ISCA, page 117-123. ACM, (1983)