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Disambiguation of "Sapatnekar, Sachin S."

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Recent Progress in the Analysis of Electromigration and Stress Migration in Large Multisegment Interconnects.

, , , , , and . ISPD, page 115-123. ACM, (2023)

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Sachin Arora

Sachin Deshmukh

Sachin Kinge

Sachin Chhatwani

Sachin Kumar

 

Other publications of authors with the same name

Fast estimation of area-delay trade-offs in circuit sizing., and . ISCAS (4), page 3575-3578. IEEE, (2005)Improving STT-MRAM density through multibit error correction., , , and . DATE, page 1-6. European Design and Automation Association, (2014)FAR-DS: Full-Plane AWE Routing with Driver Sizing., and . DAC, page 84-89. ACM Press, (1999)Low-power clock distribution using multiple voltages and reduced swings., and . IEEE Trans. Very Large Scale Integr. Syst., 10 (3): 309-318 (2002)A Simple Yet Efficient Accuracy-Configurable Adder Design., , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (6): 1112-1125 (2018)Optimizing Decoupling Capacitors in 3D Circuits for Power Grid Integrity., , and . IEEE Des. Test Comput., 26 (5): 15-25 (2009)Stress-Induced Performance Shifts in Flexible System-in-Foils Using Ultra-Thin Chips., and . ISQED, page 237-242. IEEE, (2020)Exploring a Machine Learning Approach to Performance Driven Analog IC Placement., , , , , , , and . ISVLSI, page 24-29. IEEE, (2020)Editorial.. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (12): 1837-1838 (2013)A Framework for Scalable Postsilicon Statistical Delay Prediction Under Process Variations., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (8): 1201-1212 (2009)