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Modeling of FPGA Local/Global Interconnect Resources and Derivation of Minimal Test Configurations.

, , and . DFT, page 284-292. IEEE Computer Society, (2002)

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Modeling of FPGA Local/Global Interconnect Resources and Derivation of Minimal Test Configurations., , and . DFT, page 284-292. IEEE Computer Society, (2002)Soft-decision decoding of convolutional codes with square-law detectors., and . IET Commun., 7 (10): 966-972 (2013)A Compact Architecture for Simulation of Spatio-Temporally Correlated MIMO Fading Channels., and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (4): 1280-1288 (2014)Parallelized QR decomposition using GPUs., and . CCECE, page 1-6. IEEE, (2019)A flexible layered architecture for accurate digital baseband algorithm development and verification., , and . DATE, page 45-50. IEEE, (2009)A Reconfigurable SOS-based Rayleigh Fading Channel Simulator., and . SiPS, page 39-44. IEEE, (2006)An Efficient Parallel Architecture for Implementing LST Decoding in MIMO Systems., and . IEEE Trans. Signal Process., 54 (10): 3899-3907 (2006)FPGA Implementation of Isotropic and Nonisotropic Fading Channels., and . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (11): 796-800 (2013)Hardware-based Error Rate Testing of Digital Baseband Communication Systems., , and . ITC, page 1-10. IEEE Computer Society, (2008)Reconfigurable performance measurement system-on-a-chip for baseband wireless algorithm design and verification., , and . IEEE Wirel. Commun., 19 (6): 84-91 (2012)