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Disambiguation of "Patra, Priyadarsan"

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Techniques for Debug of Low Power SoCs.

, , , , , , , , , and . MTV, page 45-49. IEEE, (2019)

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Cecilia-Carmen Patrascan

Patra Charalampaki

Reena Patra

Pintu Patra

Amiya Kumar Patra

 

Other publications of authors with the same name

Delay Insensitive Logic for RSFQ Superconductor Technology., , and . ASYNC, page 42-53. IEEE Computer Society, (1997)Observability-aware Directed Test Generation for Soft Errors and Crosstalk Faults., , and . VLSI Design, page 291-296. IEEE Computer Society, (2013)Bee Colony Inspired Metamodeling Based Fast Optimization of a Nano-CMOS PLL., , , and . ISED, page 6-11. IEEE Computer Society, (2011)Double Layer Perceptron Synchronized Computational Intelligence Guided Fractal Triangle Based Cryptographic Technique for Secured Communication (DLPFT)., , and . ISED, page 191-195. IEEE Computer Society, (2013)A System-Level Solution to Domino Synthesis with 2 GHz Application., , , , , , , , , and 2 other author(s). ICCD, page 164-. IEEE Computer Society, (2002)Dynamic Selection of Trace Signals for Post-Silicon Debug., , , , and . MTV, page 62-67. IEEE Computer Society, (2013)Fabrics on Die: Where Function, Debug and Test Meet., and . NOCS, page 4:1-4:3. ACM, (2015)Power-efficient delay-insensitive codes for data transmission., and . HICSS (1), page 316-323. IEEE Computer Society, (1995)Efficient building blocks for delay insensitive circuits., and . ASYNC, page 196-205. IEEE, (1994)On the cusp of a validation wall.. IEEE Des. Test Comput., 24 (2): 193-196 (2007)