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Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units.

, , , , и . SAMOS, том 3133 из Lecture Notes in Computer Science, стр. 88-97. Springer, (2004)

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Javier Manero

Javier Jáurequi

Javier Dreyer

Javier Papa

Javier Arpón

 

Другие публикации лиц с тем же именем

Modulo scheduling with integrated register spilling for clustered VLIW architectures., , , и . MICRO, стр. 160-169. ACM/IEEE Computer Society, (2001)Two-level hierarchical register file organization for VLIW processors., , , и . MICRO, стр. 137-146. ACM/IEEE Computer Society, (2000)Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes., , , , и . ISHPC, том 2858 из Lecture Notes in Computer Science, стр. 113-126. Springer, (2003)Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units., , , , и . SAMOS, том 3133 из Lecture Notes in Computer Science, стр. 88-97. Springer, (2004)Improved spill code generation for software pipelined loops., , , и . PLDI, стр. 134-144. ACM, (2000)MIRS: Modulo Scheduling with Integrated Register Spilling., , , и . LCPC, том 2624 из Lecture Notes in Computer Science, стр. 239-253. Springer, (2001)Hierarchical Clustered Register File Organization for VLIW Processors., , , и . IPDPS, стр. 77. IEEE Computer Society, (2003)