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Disambiguation of "Shan, Weiwei"

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AAD-KWS: a sub-µW keyword spotting chip with a zero-cost, acoustic activity detector from a 170nW MFCC feature extractor in 28nm CMOS.

, , , and . ESSCIRC, page 99-102. IEEE, (2021)

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Weiwei Tian

Weiwei Chen

Shan-Shan Zhan

Weiwei Cheng

Weiwei Wang

 

Other publications of authors with the same name

A Side-channel Analysis Resistant Reconfigurable Cryptographic Coprocessor Supporting Multiple Block Cipher Algorithms., , , , , , , and . DAC, page 176:1-176:6. ACM, (2014)VLSI design of a reconfigurable S-box based on memory sharing method., , , and . IEICE Electron. Express, 11 (1): 20130872 (2014)IVATS: A Leakage Reduction Technique Based on Input Vector Analysis and Transistor Stacking in CMOS Circuits., , and . ISCAS, page 1-5. IEEE, (2023)HTD: A light-weight holosymmetrical transition detector based in-situ timing monitoring technique for wide-voltage-range in 40nm CMOS., , , and . A-SSCC, page 209-212. IEEE, (2017)A 0.44V-1.1V 9-transistor transition-detector and half-path error detection technique for low power applications., , , , and . A-SSCC, page 205-208. IEEE, (2017)A 0.46V-1.1V Transition-Detector with In-Situ Timing-Error Detection and Correction Based on Pulsed-Latch Design in AES Accelerator., , , , , , and . A-SSCC, page 1-4. IEEE, (2018)A Depthwise Separable Convolution Neural Network for Small-footprint Keyword Spotting Using Approximate MAC Unit and Streaming Convolution Reuse., , and . APCCAS, page 309-312. IEEE, (2019)An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator without Accuracy Loss in 28nm CMOS., , , , and . A-SSCC, page 1-3. IEEE, (2021)Short-path Padding Method for Timing Error Resilient Circuits based on Transmission Gates Insertion., , and . ACM Great Lakes Symposium on VLSI, page 105-110. ACM, (2018)Using Wind Turbines for Providing Defined Levels of Synthetic Inertia in System Split Scenarios., , and . ISGT-Europe, page 829-833. IEEE, (2020)