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20.3 A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS., , , , , , , , , и . ISSCC, стр. 1-3. IEEE, (2015)DDR4 transmitter with AC-boost equalization and wide-band voltage regulators for thin-oxide protection in 14-nm SOI CMOS technology., , , , , , , , , и 1 other автор(ы). ESSCIRC, стр. 115-118. IEEE, (2017)Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver., , , , , , , , , и 3 other автор(ы). ISCAS, стр. 1-5. IEEE, (2018)A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET., , , , , , , , , и 6 other автор(ы). A-SSCC, стр. 239-240. IEEE, (2019)A 4×4 MIMO Discrete Multitone Wireline Transceiver With Far-End Crosstalk Cancellation For ADC-Based High-Speed Serial Links., , , , , , , , , и . ISCAS, стр. 1-5. IEEE, (2024)A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links., , , , , , , , , и 14 other автор(ы). VLSI Technology and Circuits, стр. 28-29. IEEE, (2022)An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS., , , , , , , , , и 17 other автор(ы). VLSI Technology and Circuits, стр. 168-169. IEEE, (2022)An 8b 1.0-to-1.25GS/s 0.7-to-0.8V Single-Stage Time-Based Gated-Ring-Oscillator ADC with $2\times$ Interpolating Sense-Amplifier-Latches., , , , , , , и . ISSCC, стр. 266-267. IEEE, (2023)A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS., , , , , , , , , и . ISSCC, стр. 468-469. IEEE, (2013)10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver., , , , , , , , , и 1 other автор(ы). ISSCC, стр. 1-3. IEEE, (2015)