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Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design.

, , , , и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 89-A (12): 3560-3568 (2006)

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Kaoru Onodera

Keiichi Onodera

Hidetoshi Yamabe

 

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