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Mind The Power Holes: Sifting Operating Points in Power-Limited Heterogeneous Multicores., , , and . IEEE Comput. Archit. Lett., 16 (1): 56-59 (2017)P-OPT: Practical Optimal Cache Replacement for Graph Analytics., , , and . HPCA, page 668-681. IEEE, (2021)BEAR: techniques for mitigating bandwidth bloat in gigascale DRAM caches., , and . ISCA, page 198-210. ACM, (2015)Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions., and . HPCA, page 191-200. IEEE Computer Society, (2005)In-Line Interrupt Handling for Software-Managed TLBs., and . ICCD, page 62-67. IEEE Computer Society, (2001)RIC: Relaxed Inclusion Caches for Mitigating LLC Side-Channel Attacks., , , , , , and . DAC, page 7:1-7:6. ACM, (2017)IDYLL: Enhancing Page Translation in Multi-GPUs via Light Weight PTE Invalidations., , , , , and . MICRO, page 1163-1177. ACM, (2023)MINT: Securely Mitigating Rowhammer with a Minimalist In-DRAM Tracker., , and . CoRR, (2024)Automatic SMT threading for OpenMP applications on the Intel Xeon Phi co-processor., , , , , and . ROSS@ICS, page 7:1-7:7. ACM, (2014)Improving the Precise Interrupt Mechanism of Software-Managed TLB Miss Handlers., and . HiPC, volume 2228 of Lecture Notes in Computer Science, page 282-293. Springer, (2001)