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Disambiguation of "Naseer, A. R."

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High Level Design Experiences with IDEAS.

, , , , , , , and . VLSI Design, page 110. IEEE Computer Society, (1993)

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R. A. A. Bowler

Aisha Naseer

M A R Meier

Federico B A A R Matousek

Felix A R Müller

 

Other publications of authors with the same name

Optimal Clock Period for Synthesized Data Paths., , and . VLSI Design, page 134-139. IEEE Computer Society, (1997)WSNodeRater - An Optimized Reputation System Framework for Security Aware Energy Efficient Geographic Routing in WSNs., and . AICCSA, page 258-265. IEEE Computer Society, (2007)SNARE: sensor node attached reputation evaluator., and . CoNEXT, page 29. ACM, (2006)Delay Minimal Mapping of RTL Structures onto LUT Based FPGAs., , and . FPL, volume 975 of Lecture Notes in Computer Science, page 139-148. Springer, (1995)FAST: FPGA Targeted RTL Structure Synthesis Technique., , and . VLSI Design, page 21-24. IEEE Computer Society, (1994)Two-way distributed sequential pattern mining using fruit fly algorithm along with Hadoop and map reduce framework., , and . Int. J. Comput. Aided Eng. Technol., 14 (4): 503-519 (2021)Adaptive Pre-task Assignment scheduling strategy for heterogeneous distributed raytracing system., , and . IEICE Electron. Express, 1 (13): 373-379 (2004)An Efficient Technique for Mapping RTL Structures onto FPGAs., , and . FPL, volume 849 of Lecture Notes in Computer Science, page 99-110. Springer, (1994)High Level Design Experiences with IDEAS., , , , , , , and . VLSI Design, page 110. IEEE Computer Society, (1993)