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Compute-Capable Block RAMs for Efficient Deep Learning Acceleration on FPGAs., , , , , , , , and . FCCM, page 88-96. IEEE, (2021)In-Memory Data Parallel Processor., , and . ASPLOS, page 1-14. ACM, (2018)Performance and power optimization through data compression in Network-on-Chip architectures., , , , , , , and . HPCA, page 215-225. IEEE Computer Society, (2008)Bit Prudent In-Cache Acceleration of Deep Convolutional Neural Networks., , , , and . HPCA, page 81-93. IEEE, (2019)A novel dimensionally-decomposed router for on-chip communication in 3D architectures., , , , , , , and . ISCA, page 138-149. ACM, (2007)A case for integrated processor-cache partitioning in chip multiprocessors., , , , and . SC, ACM, (2009)Trace based phase prediction for tightly-coupled heterogeneous cores., , , and . MICRO, page 445-456. ACM, (2013)ASPEN: A Scalable In-SRAM Architecture for Pushdown Automata., , , , , , and . MICRO, page 921-932. IEEE Computer Society, (2018)A 2.46M reads/s Genome Sequencing Accelerator using a 625 Processing-Element Array., , , , , , , , , and 1 other author(s). CICC, page 1-4. IEEE, (2020)Parallel Automata Processor., and . ISCA, page 600-612. ACM, (2017)