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VL-ECC: Variable Data-Length Error Correction Code for Embedded Memory in DSP Applications.

, , and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (2): 120-124 (2014)

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Customized SRAM design for low power video code applications., , , and . ISOCC, page 79-80. IEEE, (2016)High performance and low power FIR filter design based on sharing multiplication., , , , , and . ISLPED, page 295-300. ACM, (2002)Low Cost Ternary Content Addressable Memory Based on Early Termination Precharge Scheme., , and . ISCAS, page 1-4. IEEE, (2019)A low power reconfigurable DCT architecture to trade off image quality for computational complexity., and . ICASSP (5), page 17-20. IEEE, (2004)Domain Wall Memory-Based Design of Deep Neural Network Convolutional Layers., , , and . IEEE Access, (2020)Dynamic Bit-Width Adaptation in DCT: An Approach to Trade Off Image Quality and Computation Energy., , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (5): 787-793 (2010)A Low Complexity Reconfigurable DCT Architecture to Trade off Image Quality for Power Consumption., and . J. Signal Process. Syst., 53 (3): 399-410 (2008)Low Cost Heterogeneous ARIA S-Box Implementation for CPA-Resistance., , and . ISCAS, page 1-5. IEEE, (2021)A Charge-domain 10T SRAM based In-Memory-Computing Macro for Low Energy and Highly Accurate DNN inference., and . ISOCC, page 89-90. IEEE, (2021)SRAM Bit-line Boosting Circuit for Low Latency and Timing Aware Read Operation., , and . ISOCC, page 5-6. IEEE, (2022)