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Disambiguation of "Maymandi-Nejad, Mohammad"

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An Ultra-low-power 10-Bit 100-kS/s Successive-approximation Analog-to-digital Converter.

, , , and . ISCAS, page 1117-1120. IEEE, (2009)

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Mohammad Nejad-Sattary

Mohammad Nazari-Nejad

Mohammad Sadegh Khakbaz-Nejad

Mohammad Pasha Tavana-Nejad

Farahnaz Nejadensan

 

Other publications of authors with the same name

A 0.8V Delta-Sigma modulator using DTMOS technique., and . ISCAS (4), page 3684-3687. IEEE, (2005)An Ultra-low-power 10-Bit 100-kS/s Successive-approximation Analog-to-digital Converter., , , and . ISCAS, page 1117-1120. IEEE, (2009)Capacitor scaling for low-power design of cyclic analog-to-digital converters., , and . ISCAS, page 1456-1459. IEEE, (2010)An ultra low-power low-voltage switched-comparator successive approximation analog to digital converter., and . IEICE Electron. Express, 6 (15): 1098-1104 (2009)A Linear Comparator-Based Fully Digital Delay Element., , , and . ISVLSI, page 652-655. IEEE Computer Society, (2015)A 0.8-V 420nW CMOS switched-opamp switched-capacitor pacemaker front-end with a new continuous-time CMFB., and . ICECS, page 758-761. IEEE, (2008)Analytical phase noise study of a back-gate coupled colpitts quadrature VCO., , , and . Microelectron. J., (2020)Analytical model for CMOS cross-coupled LC-tank oscillator., and . IET Circuits Devices Syst., 8 (1): 1-9 (2014)Nonautoregressive Nonlinear Identification of IPMC in Large Deformation Situations Using Generalized Volterra-Based Approach., , and . IEEE Trans. Instrumentation and Measurement, 65 (12): 2866-2872 (2016)A Novel Overlap-Based Logic Cell: An Efficient Implementation of Flip-Flops With Embedded Logic., and . IEEE Trans. Very Large Scale Integr. Syst., 18 (2): 222-231 (2010)