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Exposing Abstraction-Level Interactions with a Parallel Ray Tracer., , , , , , , , , and 7 other author(s). WCAE@ISCA, page 5:1-5:8. ACM, (2019)Exploiting reuse locality on inclusive shared last-level caches., , , and . ACM Trans. Archit. Code Optim., 9 (4): 38:1-38:19 (2013)Near-optimal replacement policies for shared caches in multicore processors., , , , and . J. Supercomput., 77 (10): 11756-11785 (2021)Boosting Backward Search Throughput for FM-Index Using a Compressed Encoding., , , , , and . DCC, page 577. IEEE, (2019)Forecasting lifetime and performance of a novel NVM last-level cache with compression., , , , and . CoRR, (2022)BALANCER: bandwidth allocation and cache partitioning for multicore processors., , , and . J. Supercomput., 79 (9): 10252-10276 (June 2023)Characterization and Improvement of Load/Store Cache-based Prefetching., , , and . International Conference on Supercomputing, page 369-376. ACM, (1998)Counteracting Bank Misprediction in Sliced First-Level Caches., , , and . Euro-Par, volume 2790 of Lecture Notes in Computer Science, page 586-596. Springer, (2003)Speeding-Up Synchronizations in DSM Multiprocessors., , , , and . Euro-Par, volume 4128 of Lecture Notes in Computer Science, page 473-484. Springer, (2006)Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage., , , , and . IEEE Trans. Computers, 65 (3): 755-769 (2016)